Senior Design Verification (DV) Engineer | Teton Electronics Inc. | Engineer Jobs in Bangladesh 2025

by Teton Electronics Inc.

in Engineer / Architects, IT / Telecommunication
Full Time
Dhaka
February 24, 2025

Job Overview

  • Date Posted
    February 24, 2025
  • Location
    Dhaka
  • Expiration date
    February 24, 2026
  • Experience
    5 Years
  • Gender
    Both
  • Industry
    Private Company
  • Qualification
    B.sc, M.sc, Bachelor Degree, Master’s Degree
  • Position Name
    Engineer

Job Description

Apply Guideline

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To apply for this job, start by Clicking Here to create a candidate profile and update your CV. Then, click the ‘Apply Now‘ button.

Teton Electronics Inc. | Senior Design Verification (DV) Engineer Job Details | Job Circular 2025:

TETON Electronics Inc., a Silicon Valley-based USA company with a wholly owned subsidiary, TETON Private Ltd, Dhaka, Bangladesh, has been developing cutting-edge electronic consumer products since 2020. The company is building a VLSI Physical Design team to develop silicon for AL/ML-based loT products. We are looking for a group of highly motivated, innovative, driven, and team-oriented engineers to work with our USA-based customers.

Job Summary

Code: EM387
Employer: Teton Electronics Inc.
Post Name: Senior Design Verification (DV) Engineer
Job Location: Dhaka 
No. of Vacancies: –
Job Type: Full Time
Job Category: Engineer / Architects
Gender: Both
Age Limitation: –
Educational Qualifications: Bachelor/ Masters/ B.Sc. / M.Sc. in EEE, EECE and CSE
Experience Requirements: At least 5 years of experience
Salary: Negotiable
Apply Procedure: Create a candidate profile and update your CV. Then, click the ‘Apply Now’ button.
Application Deadline: March 24, 2025

 

Job Responsibilities:

  • Feature extraction from Specification and develop SoC/ASIC level verification plan.
  • Architect and create verification environments using System Verilog and Universal verification methodology (UVM) for SoC/ASIC.
  • Hands-on experience developing SystemVerilog OVM/UVM verification environment from scratch, including agents, monitors, drivers, and scoreboards is a plus.
  • Lead a team in developing a self-checking Testbench using Verilog, and System Verilog to validate RTL designs in block and SoC levels.
  • Lead a team in developing test cases and checkers according to the verification plan to achieve the desired functional and code coverage level.
  • Tests and sequences development with constraint random stimulus.
  • Develop and run block-level and system-level tests to verify system functionality functionality.
  • SVA generation and UVM RAL development flow and integration.
  • Third-party (Synopsys, Cadence, Mentor) VIP integration.
  • Lead engineers to develop scripts and run regression simulations.
  • Experience in communicating with USA-based customer design teams is a plus.

Other Facilities:

  • Flexible working hours (8 AM to 4 PM, Mon – Fri)
  • Friendly and creative work environment
  • Fully Subsidized Lunch from the office
  • Transportation facility (As per company policy)
  • Yearly two festival bonuses
​​​​​​​​​​​​​​Additional requirements: 
  • Minimum of 5 years of experience Have good knowledge of the VLSI field.
  • Vast knowledge of Analog and Digital Circuit Design and Analysis. Proficiency in Verilog/VHDL / SystemVerilog.
  • A strong concept of any Procedural Programming Language such as C, SystemC, etc. Object-oriented programming concepts such as C++, Java, Python, etc. is a plus.
  • Knowledge of CAD tools like Cadence IUS, Synopsys VCS, and Mentor Questa is a plus.
  • Knowledge of Linux operating systems is a plus.
  • Knowledge of Python, Perl, and Bash scripting is a plus.​​​​​​​
Benefits
  • Festival bonus
  • Annual salary review

  • Tour allowance

Apply Procedure:

Create a candidate profile and update your CV. Then, click the ‘Apply Now’ button

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